In order to reduce the size and power consumption of a radio receiver or integrate an analog signal processor with a digital signal processor, a configuration that directly samples a high frequency signal at discrete times to perform a discrete time process on the subsequent stage has been proposed (for example, Non-Patent Document 1). This configuration is expected to reduce the design complexity of a continuous-time analog process according to the related art.
Hereinafter, an example of the configuration and operation of a radio receiver using the discrete time process according to the related art will be described with reference to FIG. 1.
Analog RF signals received by antenna 10 are amplified by low noise amplifying section (LNA) 20. The amplified analog RF signals are converted into low frequency signals and discrete time analog signals by DISCRETE TIME FREQUENCY CONVERTER 30. At this time, conversion is performed with a sampling rate, which determines a discrete time interval, low enough to process the signal in the subsequent stage.
Specifically, sampling mixer 31 mixes a local signal with a frequency fLO supplied from LOCAL FREQUENCY OSCILLATOR 40 with the signal outputted from low noise amplifying section 20 to convert the frequency of the received analog RF signal and also convert the continuous-time signal into a discrete time signal.
The obtained discrete time signal has a sampling rate equivalent to the local frequency fLO, which causes a large load to be applied to the subsequent stage. Therefore, DECIMATOR 32 decimates the sampling value to lower the sampling rate. In addition, although not shown in the drawings, it goes without saying that the influence of aliasing distortion generated due to the decimation should be removed in the previous stage.
The discrete time analog signal decimated to a sampling rate of fLO/N is quantized by A/D CONVERTER 50 at the sampling rate of fLO/N to be converted into a digital value. Then, DIGITAL RECEIVING PROCESSOR 60 in the subsequent stage performs predetermined reception processes, such as demodulation and decoding processes, on the digital signal, and outputs the processed signal as received data.
By converting the received analog RF signal into a discrete time signal and performing discrete time signal processing on the discrete time signal in this way, it is possible to apply a digital signal processing design, and thus it is possible to reduce the complexity of an analog circuit according to the related art. As a result, it is possible to easily design a radio receiver and reduce the size thereof.
FIG. 1 shows a general configuration example of a radio receiver and according to required specifications of a radio communication system used, a filter may be inserted in previous stage of low noise amplifying section 20 or a delta-sigma (ΔΣ) A/D CONVERTER may be used as A/D CONVERTER 50.
Non-Patent Document 1 discloses a configuration in which a processing section corresponding to DECIMATOR 32 has the filtering effect by discrete time charge movement.
Non-patent Document 1: R. B. Staszewski, et al., “All-Digital TX Frequency Synthesizer and Discrete time Receiver for Bluetooth Radio in 130 n-nm CMOS”, IEEE Journal of Solid-State Circuits, VOL. 39, NO. 12, December 2004 (pp. 2284 to 2287, and FIG. 12 to FIG. 16)